1. Field of the Invention
The present invention relates to a logic simulator which functions to determine characteristic data of wiring loads of a logic circuit formed by a predetermined layout pattern.
2. Description of the Background Art
FIG. 16 is a block diagram of a conventional wiring load extractor for an RC model. A wiring load model generator 11 receives a wiring layout (pattern) data D1 which forms a logic circuit to generate a wiring load model circuit data D2, which is outputted to a wiring distributed constant circuit calculator 12.
FIG. 17 illustrates an example of the wiring layout data D1. In FIG. 17, reference numerals 21 to 23 designate inverters; 24 (24a to 24c) designates a wiring formed between an output of the inverter 21 and inputs of the inverters 22 and 23; reference character N1 designates branch point of the wiring 24; and 31 and 32 designate other adjacent wirings which are not directly connected to the wiring 24.
The wiring load model generator 11, where receiving the wiring layout data D1 shown in FIG. 17, divides the wiring 24 at the branch point N1 into divided wiring regions 24a, 24b and 24c, to output the wiring load model circuit data D2 including wiring load models 25a to 25c for the divided wiring regions 24a to 24c respectively, as shown in FIG. 18.
The wiring distributed constant circuit calculator 12 receives the wiring load model circuit data D2 and a unit length wiring characteristic data D3 and multiplies the wiring length of the respective wiring load models in the wiring load model circuit data D2 by the unit length wiring characteristic data D3, to thereby calculate distributed constants (resistance R and capacitance C) which are the characteristic data of the respective wiring load models and output a distributed constant circuit data D4.
As a function of the distributed constant circuit data D4, a delay time calculator not shown calculates a signal propagation delay time of the logic circuit for the RC model.
When the wiring load models are formed on the wiring, the wiring load extractor in the conventional logic simulator thus structured disregards the presence of other adjacent wirings which are not directly connected to the wiring in calculation of the characteristic data of the wiring load models. In the wiring layout data D1 shown in FIG. 17, for example, the distributed constants of the wiring load models 25a to 25c are determined without consideration of the presence of the adjacent wirings 31 and 32 which are not directly connected to the wiring 24.
In practice, however, inter-wiring parasitic elements which lie between the wiring and its adjacent wirings cause the distributed constants of the wiring to change. Hence there arises a problem that the distributed constants of the wiring load models calculated by the conventional method are inaccurate, resulting in the inaccurate signal propagation delay time calculated by using the distributed constants. This problem tends to be not negligible since recent advances in manufacturing process decrease intervals between adjacent wirings.